Modern semiconductor devices require a precise degree of timing closure between various signals entering, being processed within and exiting the device. Generally, this requires interposing a pre-determined delay on various signals before they are further processed or presented to the outside world.
Typically, delay chains have been used, on-chip, to impose delays on such signals. In a typical straightforward approach, a plurality of logic gates, each having an inherent propagation delay, are connected (strung) together in a chain (in series) to effect an overall delay from the input of the string to the output of the string according to the number of interconnected gates in the chain. In semiconductor devices, this means that each delay chain must be pre-configured, and its overall delay remains fixed. Further, as semiconductor devices and their individual gates are becoming faster and faster, an enormous number of gates may need to be interconnected to achieve the desired delay in a particular delay chain for a particular signal, since the delay through each gate is related to the "inherent" switching speed of the device. In some instances, the overall number of gates needed to implement various delays in the semiconductor device may become quite large, seriously adversely impact the number of gates remaining for implementing the desired functionality for the device. Design time is also wasted on implementing various delay chains, the desired configuration of which may change during the design process as a result of device (e.g. logic) simulation and/or specification changes.
What is needed is a readily configurable delay generator that can be applied to various semiconductor technologies.
U.S. Pat. No. 3,539,926 discloses a digitally programmable monostable multivibrator wherein a high frequency oscillator (18) is keyed into oscillation by an incoming signal. The output of the oscillator initiates a counting process in a binary counter. The binary counter comprises a series of flip-flops corresponding to powers of two (2.sup.n). A manually-selected switch (19) selectively enables gates (G10-G16), each gate connected to one of the flip-flops, in order that a signal that will terminate the operation of the oscillator (18). Apparently, the "resolution" of the time interval between the oscillator commencing and terminating oscillation is limited to powers of two times the oscillation frequency. Further, the oscillation frequency appears to be fixed. Further, there is no suggestion in this patent of using the pulsed output of the multivibrator in the context addressed by the present invention.
U.S. Pat. No. 3,840,815 discloses a programmable pulse width generator. The width of a first pulse, having a pre-determined width, is sequentially increased or decreased by increments corresponding to the combination of shorter pulses. A sequence of constant width pulses may also be generated.
U.S. Pat. No. 4,257,108 discloses a pulse generator for generating pulse groups with desired width and spacing, primarily directed to use in radar systems. A control frequency is derived, e.g. from a crystal oscillator, and the width and spacing of the pulse groups is controlled by PROM memories in the system.
U.S. Pat. No. 4,415,861 discloses a programmable pulse generator which generates a pulse having programmable leading and trailing edges. An oscillator starts to generate a pulse in response to a trigger signal, and the pulse is counted by a counter. Upon detection of the trailing edge of the pulse, the oscillation of the oscillator is stopped.
U.S. Pat. No. 4,441,037 discloses an internally gated variable pulsewidth clock generator which is able to provide output clock signals with the same rise rate as an external driving clock, and is particularly directed to the provision of timing signals in a digital display unit. An integrated circuit (20) is illustrated in FIG. 5 in which are implemented one or more clock generators (21A-21C). A clock generator (21) is illustrated in FIG. 6, and employs a double bootstrap configuration of gates (29 and 30) having different capacitances, and hence different discharge times. Due to a dynamic latch action, an output signal is not allowed to go low until an applied input signal goes low.
U.S. Pat. No. 4,488,062 discloses a pulse shaper having a periodically reversing capacitor for pulse shaping.
U.S. Pat. No. 4,509,494 discloses a pulse width control circuit receiving a periodic input signal and controlling the width of an output pulse by means of a negative feedback loop, the amount of negative feedback being varied in response to a detected voltage. Applicability to an ignition unit for internal combustion engines is noted.
U.S. Pat. No. 4,675,546 discloses an edge-programmable timing signal generator for generating timing signals having complete edge programmability for accommodating incrementally-adjustable variable pulse widths. A counter (1), clock (2) and memory circuit (3) form a coarse timing circuit (5) for generating a (coarse) timing signal having pulse widths which are variable by coarse time increments. The output of the coarse timing circuit is connected to a delay register (7) for delaying the generated coarse timing signal. The output of the coarse timing circuit is also applied to rising edge and falling edge delay lines (9 and 11.) By inverting signals input to the rising and falling edge delay lines, rising and falling edges are generated at any time during the period of the coarse timing signal.
U.S. Pat. No. 4,754,163 discloses a pulse generator with adjustable pulse frequency, pulse width and pulse delay. The output pulses of a start-stop oscillator, having a fixed operating frequency, are counted by a counter in adjustable counting cycles.